1) Field of the Invention
The present invention relates to a technique for selecting a net/wiring whose layout is to be changed for improving a delay in connection with a technique for designing a semiconductor device; particularly, a large-scale integrated circuit (LSI), as well as to a technique for selecting a net/wiring whose layout is to be changed for improving a delay and changing the layout of the thus-selected net/wiring.
2) Description of the Related Art
Various techniques for arranging or wiring a net or a wiring in an optimum state have hitherto been proposed in connection with a technique for designing a semiconductor device (see Patent Documents 1 and 2 provided below).
For instance, Patent Document 1 discloses a technique for making an attempt to reduce the power consumed by circuitry by means of optimizing a wiring width on the basis of a slack value. Patent Document 2 discloses a technique for designing a package on the basis of a delay value for improving a delay.
However, a wiring delay has recently increased in comparison with a gate delay, as a result of miniaturization of a semiconductor device; particularly, a large-scale integrated circuit (LSI). Of the wiring capacitances that are prime causes of a wiring delay, a wiring capacitance [hereinafter called an inter-wiring capacitance (Δc)] existing between a wiring and another wiring adjacent thereto is higher than a wiring capacitance existing between a wiring and a substrate.
Therefore, even when at the time of designing of a miniaturized LSI an attempt is made to solve a wiring delay on the basis of a mere delay value, as described in Patent Document 2, difficulty is encountered in reliably improving a wiring delay. Further, it is desirable to change the layout of a net/wiring having a large inter-wiring capacitance (Δc) such that the inter-wiring capacitance is curtailed.
In connection with designing of a semiconductor integrated circuit, there has been proposed a technique for changing the layout of a wiring, in consideration of the inter-wiring capacitance for improving a delay (see Patent Documents 3 and 4 provided below).
[Patent Document 1] Japanese Patent Application Laid-Open No. HEI 7-93386
[Patent Document 2] Japanese Patent Application Laid-Open No. HEI 7-263559
[Patent Document 3] Japanese Patent Application Laid-Open No. HEI 10-313058
[Patent Document 4] Japanese Patent Application Laid-Open No. 2002-280454
However, according to the technique that is described in Patent Documents 3 and 4 and that uses inter-wiring capacitances registered in a table beforehand while taking lengths of adjacent wirings and cross rates as parameters, an inter-wiring capacitance cannot be determined with high accuracy. As a result, a wiring whose delay should be improved cannot be selected reliably or efficiently.